0dMIPS

In order 5-stages pipeline MIPS64r6 SoC implementation with peripheral components, simulated and tested with Verilator.

Dependenices

• mips64el-linux-gnu-binutils toolchains(as and objdump), they're under mips64el-linux-gnu-binutils in Arch.
• [OPTIONAL] If you like to write C directly, I mainly use mips64el-linux-gnu-gcc-bootstrap with musl as sysroot. Use scripts/install_mips64el_musl.sh to download musl and mips64el-linux-gnu-gcc-bootstrap.
• verilator https://github.com/verilator/verilator for simulations.
• [OPTIONAL] sdl3 https://github.com/libsdl-org/SDL for any simulation with VGA output.
• [OPTIONAL] lcov https://github.com/linux-test-project/lcov for gather coverage data.
• [OPTIONAL] capstone https://github.com/capstone-engine/capstone for show disassembly in debugger TUI.

How to run

1. cmake -B build .
2. cmake --build build -j ${$(nproc)-1} to build all. All binaries are placed under build/bin
3. cmake --build build --target help to list all targets
4. ./runAllTest.sh to run all generated tests under build/bin(by cmake), and use DUMP_COV=1 ./runAllTest.sh to dump coverage data
5. cmake --build build --target <script_name> to compile script into memory.dat, e.g. fibonacci

Plan

• Basic 5-stages pipeline
• TUI GDB-style debugger (simulated)
• Peripherals by MMIO
  • UART
  • VGA
  • Timer
  • mock stdout
• Cache
  • L1 inst & data cache and arbiter
• Interrupts
  • Timer interrupt
  • Break
  • Syscall
• out-of-order execution double-issue in-order
• AXI
  • Memory
• Branch prediction
• Multiplier/Divider
• FPU(cp1)

Demo

Hello world with debugger (asciinema)

Simulation file structure

• debugger_tui GDB-style TUI debugger with information about pipeline(disassembly by capstone), registers, memory, peripherals.
• SOC_debug enable debug print and press any key to step.
• SOC_sim run simulation under info log.
• SOC_run_sim run simulation without info log.
• SOC_VGA_sim run simulation with VGA output(provided by SDL3).
• VGA_sim run demo VGA simulation.

Schematic diagram

WIP