Add MaxLinear GSW1xx DSA driver support #1386
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| /* | ||
| * Copyright (c) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997 | ||
| * The Regents of the University of California. All rights reserved. | ||
| * | ||
| * Redistribution and use in source and binary forms, with or without | ||
| * modification, are permitted provided that: (1) source code distributions | ||
| * retain the above copyright notice and this paragraph in its entirety, (2) | ||
| * distributions including binary code include the above copyright notice and | ||
| * this paragraph in its entirety in the documentation or other materials | ||
| * provided with the distribution, and (3) all advertising materials mentioning | ||
| * features or use of this software display the following acknowledgement: | ||
| * ``This product includes software developed by the University of California, | ||
| * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of | ||
| * the University nor the names of its contributors may be used to endorse | ||
| * or promote products derived from this software without specific prior | ||
| * written permission. | ||
| * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED | ||
| * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF | ||
| * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. | ||
| */ | ||
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| /* based on print-dsa.c */ | ||
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| /* \summary: MaxLinear (Ethertype) Distributed Switch Architecture */ | ||
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| #ifdef HAVE_CONFIG_H | ||
| #include <config.h> | ||
| #endif | ||
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| #include "netdissect-stdinc.h" | ||
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| #include "netdissect.h" | ||
| #include "ethertype.h" | ||
| #include "addrtoname.h" | ||
| #include "extract.h" | ||
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| /* | ||
| * Ingress and Egress have different formats. | ||
| * | ||
| * Format of (Ethertyped) Ingress tagged frames: | ||
| * | ||
| * 0 +----+----+----+----+----+----+----+----+ | ||
| * | Ether Destination Address | | ||
| * +6 +----+----+----+----+----+----+----+----+ | ||
| * | Ether Source Address | | ||
| * +6 +----+----+----+----+----+----+----+----+ +- | ||
| * | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| * +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| * | Prog. DSA Ether Type [7:0] | | + | ||
| * +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| * |PME[7] TCE[6] TSE[5] FNL[4] TTC[3:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | TEPML [7:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | TEPMH [7:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | Res[7:5] IE[4] SP[3:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | Res [7:0] all zero | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | Res [7:0] all zero | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ +- +- | ||
| * | ||
| * Format of (Ethertyped) Egress tagged frames: | ||
| * | ||
| * 0 +----+----+----+----+----+----+----+----+ | ||
| * | Ether Destination Address | | ||
| * +6 +----+----+----+----+----+----+----+----+ | ||
| * | Ether Source Address | | ||
| * +6 +----+----+----+----+----+----+----+----+ +- | ||
| * | Prog. DSA Ether Type [15:8] | | (8-byte) Special Tag | ||
| * +1 +----+----+----+----+----+----+----+----+ | Contains a programmable Ether type. | ||
| * | Prog. DSA Ether Type [7:0] | | + | ||
| * +1 +----+----+----+----+----+----+----+----+ | | (6-byte) Special Tag Content | ||
| * | TC[7:4] IPN [3:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | PPPOE[7] IPV[6] IPO[5:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | DLPML [7:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | DLPMR [7:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | MI[7] KL2UM[6] PLHB[5:0] | | | | ||
| * +1 +----+----+----+----+----+----+----+----+ | | | ||
| * | PLLB [7:0] | | | | ||
| * +2 +----+----+----+----+----+----+----+----+ +- +- | ||
| * . . . . . . . . . | ||
| * | ||
| * PME: Port map enable | ||
| * IPN: Ingress port number | ||
| * TCE: Traffic class enable | ||
| * TSE: Time stamp enable | ||
| * FNL: Force no learning | ||
| * TC: Traffic class | ||
| * IPV: IPv4 packet | ||
| * IPO: IP offset | ||
| * SP: Source port | ||
| * IE: Interrupt enable | ||
| * PPPOE: ppp-over-ethernet | ||
| * DLPML: Destination logical port map low bits. | ||
| * DLPMR: Destination logical port map high (reserved) | ||
| * MI: Mirror indication | ||
| * KL2UM Known l2 unicast/multicast mac. | ||
| * PLHB: Packet Length High Bits | ||
| * PLLB: Packet Length Low Bits. | ||
| * TEPML: Target egress port maps low bits | ||
| * TEPMH: Target egress port maps high bits (reserved) | ||
| * Res: Reserved | ||
| */ | ||
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| #define TOK(tag, byte, mask, shift) ((GET_U_1(&(((const u_char *) tag)[byte])) & (mask)) >> (shift)) | ||
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| #define GSW1XX_ET1(tag) TOK(tag, 0, 0xFF, 0) | ||
| #define GSW1XX_ET2(tag) TOK(tag, 1, 0xFF, 0) | ||
| #define GSW1XX_TTC(tag) TOK(tag, 2, 0x08, 0) | ||
| #define GSW1XX_IG_PME(tag) TOK(tag, 2, 0x80, 7) | ||
| #define GSW1XX_IG_TCE(tag) TOK(tag, 2, 0x40, 6) | ||
| #define GSW1XX_IG_TSE(tag) TOK(tag, 2, 0x20, 5) | ||
| #define GSW1XX_IG_FNL(tag) TOK(tag, 2, 0x10, 4) | ||
| #define GSW1XX_IG_SP(tag) TOK(tag, 2, 0x0F, 0) | ||
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Member
There was a problem hiding this comment. As far as the packet diagram shows it, the offset for SP is 5, not 2. |
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| #define GSW1XX_IG_IE(tag) TOK(tag, 5, 0x10, 3) | ||
| #define GSW1XX_EG_IPN(tag) TOK(tag, 2, 0x0F, 0) | ||
| #define GSW1XX_EG_TC(tag) TOK(tag, 2, 0xF0, 4) | ||
| #define GSW1XX_EG_POE(tag) TOK(tag, 2, 0x80, 7) | ||
| #define GSW1XX_EG_IV4(tag) TOK(tag, 2, 0x40, 6) | ||
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Member
There was a problem hiding this comment. Both PPPOE and IPV are in byte 3, not 2. |
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| #define GSW1XX_EG_IPO(tag) TOK(tag, 3, 0x3F, 0) | ||
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| #define GSW1XX_MAP_LOW(tag) TOK(tag, 3, 0xFF, 0) | ||
| #define GSW1XX_MAP_HIGH(tag) TOK(tag, 4, 0xFF, 0) | ||
| #define GSW1XX_MAP(tag) ((GSW1XX_MAP_HIGH(tag) << 8) + GSW1XX_MAP_LOW(tag)) | ||
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Member
There was a problem hiding this comment. DLPML is byte 4, not 3; DLPMR is byte 5, not 4. If DLPMR is reserved, it would be best to leave it alone instead of interpreting it as the high part of the port map.
Member
There was a problem hiding this comment. Or rather the actual problem here seems to be that both ingress and egress frames have a "port map" field, which for ingress is called TEPML and is the byte at offset 3, and for egress is called DLPML and is the byte at offset 4. This way, these should be two separate macros saying whether it is ingress or egress and which map it is (for example, |
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| #define GSW1XX_LEN_LOW(tag) TOK(tag, 7, 0xFF, 0) | ||
| #define GSW1XX_LEN_HIGH(tag) TOK(tag, 6, 0x3F, 0) | ||
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Member
There was a problem hiding this comment. Is there any reason not to print the MI and KL2UM bits of byte 6? |
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| #define GSW1XX_LEN(tag) ((GSW1XX_LEN_HIGH(tag) << 8) + GSW1XX_LEN_LOW(tag)) | ||
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| #define SPTAG_LEN 8 | ||
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| static void | ||
| tag_common_print(netdissect_options *ndo, const u_char *p) | ||
| { | ||
| if (ndo->ndo_eflag ) { | ||
| int egress = !!GSW1XX_LEN(p); | ||
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| if (egress) { | ||
| ND_PRINT("Egress Port %d,", GSW1XX_EG_IPN(p)); | ||
| if (ndo->ndo_eflag > 1) { | ||
| ND_PRINT("TTC %d,", GSW1XX_TTC(p)); | ||
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Member
There was a problem hiding this comment. Regarding this and other fields: the convention is to have a space after a comma, the value is unsigned, so
Member
There was a problem hiding this comment. Also regarding this specific line, TTC does not exist in egress frames. |
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| ND_PRINT("TC %d,", GSW1XX_EG_TC(p)); | ||
| ND_PRINT("IPN %d,", GSW1XX_EG_IPN(p)); | ||
| ND_PRINT("POE %d,", GSW1XX_EG_POE(p)); | ||
| if (GSW1XX_EG_IPO(p)) { | ||
| ND_PRINT("IV4 %d,", GSW1XX_EG_IV4(p)); | ||
| ND_PRINT("IPO %d,", GSW1XX_EG_IPO(p)); | ||
| } | ||
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Member
There was a problem hiding this comment. After IPO and before the frame length it would be useful to print DLPML (using |
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| ND_PRINT("Len %d,", GSW1XX_LEN(p)); | ||
| } | ||
| } else { | ||
| ND_PRINT("Ingress Port %d,", GSW1XX_IG_SP(p)); | ||
| ND_PRINT("MAP %d,", GSW1XX_MAP(p)); | ||
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Member
There was a problem hiding this comment. If DLPML is a bitmap rather than an integer, it should be printed using
Member
There was a problem hiding this comment. Correction: for ingress frames the port map is TEPML, but the other point still applies. |
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| if (ndo->ndo_eflag > 1) { | ||
| ND_PRINT("PME %d,", GSW1XX_IG_PME(p)); | ||
| ND_PRINT("TCE %d,", GSW1XX_IG_TCE(p)); | ||
| ND_PRINT("TTC %d,", GSW1XX_TTC(p)); | ||
| ND_PRINT("FNL %d,", GSW1XX_IG_FNL(p)); | ||
| ND_PRINT("IE %d,", GSW1XX_IG_IE(p)); | ||
| ND_PRINT("TSE %d,", GSW1XX_IG_TSE(p)); | ||
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Member
There was a problem hiding this comment. Indentation is off at this line. |
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| } | ||
| } | ||
| } | ||
| } | ||
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| static void | ||
| gsw1xx_tag_print(netdissect_options *ndo, const u_char *bp) | ||
| { | ||
| const u_char *p = bp; | ||
| uint16_t sptag_etype; | ||
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| sptag_etype = GET_BE_U_2(p); | ||
| if (ndo->ndo_eflag > 2) { | ||
| ND_PRINT("MaxLinear ethertype 0x%04x (%s), ", sptag_etype, | ||
| tok2str(ethertype_values, "Unknown", sptag_etype)); | ||
| } else { | ||
| if (sptag_etype == ETHERTYPE_GSW1XX) | ||
| ND_PRINT("GSW1XX "); | ||
| else | ||
| ND_PRINT("GSW1XX Unknown 0x%04x, ", sptag_etype); | ||
| } | ||
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Member
There was a problem hiding this comment. What is the purpose of this differentiation based on |
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| tag_common_print(ndo, p); | ||
| } | ||
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| void | ||
| gsw1xx_if_print(netdissect_options *ndo, const struct pcap_pkthdr *h, const u_char *p) | ||
| { | ||
| u_int caplen = h->caplen; | ||
| u_int length = h->len; | ||
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| ndo->ndo_protocol = "gsw1xx"; | ||
| ndo->ndo_ll_hdr_len += | ||
| ether_switch_tag_print(ndo, p, length, caplen, gsw1xx_tag_print, SPTAG_LEN); | ||
| } | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,3 @@ | ||
| 1 2025-12-04 14:15:35.163012 b8:a4:4f:fc:53:8a > 01:00:5e:00:00:fb, GSW1XX Ingress Port 0,MAP 2,ethertype IPv4 (0x0800), length 362: 192.168.0.240.5353 > 224.0.0.251.5353: 0*- [0q] 3/0/4 (Cache flush) PTR axis-b8a44ffc538a.local., (Cache flush) PTR axis-b8a44ffc538a.local., (Cache flush) PTR axis-b8a44ffc538a.local. (312) | ||
| 2 2025-12-04 14:15:35.163727 b8:a4:4f:fc:53:8a > 1c:fd:08:7c:0a:e1, GSW1XX Ingress Port 0,MAP 2,ethertype IPv4 (0x0800), length 214: 192.168.0.240.22 > 192.168.0.1.43256: Flags [P.], seq 3228238683:3228238823, ack 1362097168, win 501, options [nop,nop,TS val 1250645671 ecr 99858784], length 140 | ||
| 3 2025-12-04 14:15:35.164152 1c:fd:08:7c:0a:e1 > b8:a4:4f:fc:53:8a, GSW1XX Egress Port 1,ethertype IPv4 (0x0800), length 74: 192.168.0.1.43256 > 192.168.0.240.22: Flags [.], ack 140, win 2529, options [nop,nop,TS val 99858794 ecr 1250645662], length 0 |
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TTC is specific to ingress frames, in egress frames these bits are IPN.
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So in practical terms this macro should be named
GSW1XX_IG_TTC.