SinglePass: add support for riscv64 target

[marxin]

The PR adds the rudimentary support for RISC-V 64-bit target into the SinglePass compiler. Even though, the code still needs some polishing and various TODOs must be addressed, the compiler can pass all (104) the spec tests.

TODOs:

• unwinding support
• FP status register - save/restore
• a general location_cmp + jmp_on_X needs polishing as RISC-V target does not provide a FLAGS register (Singlepass: refactor condition jumps to single fn (jmp_on_condition) #5750).
• spec/address.wast is flaky (sometimes trap is not properly triggered)
• basic testing - all compiler tests (including the WASI tests) are green now
• include RISCV-V in CI by running the tests in qemu

Minor improvements:

• CLZ, CTZ and POPCOUNT have sub-optimal performance - could be implemented as builtins in the run-time (fn call overhead)
• still some unimplemented entry points for the Machine trait - wipe unused entry points in the Trait
• more intensive testing needed (including real hardware + valgrind)

[marxin]

@syrusakbary The PR is basically ready to be merged. However, it depends on a smaller tweaks to the CI when it comes to testing of riscv64gc target: #5817 #5815 #5809

[marxin]

The CI job Run WAST tests on linux-riscv64 is green when running in CI under QEMU. Yay!

[Copilot]

Pull Request Overview

This PR adds experimental RISC-V 64-bit support to the Wasmer SinglePass compiler, enabling WebAssembly compilation for RISC-V architecture. The implementation includes core instruction encoding, trap handling, unwinding support, and comprehensive test coverage.

Key changes:

• New RISC-V machine backend with full instruction set implementation (6219 lines)
• Trap handling and unwinding support for RISC-V architecture
• CI/CD integration with QEMU-based testing for RISC-V target
• Test suite adaptations for RISC-V-specific limitations (jump instruction range)

Reviewed Changes

Copilot reviewed 23 out of 26 changed files in this pull request and generated 3 comments.

Show a summary per file

File	Description
lib/compiler-singlepass/src/machine_riscv.rs	Core RISC-V machine implementation with instruction encoding and code generation
lib/compiler-singlepass/src/riscv_decl.rs	RISC-V register definitions and calling convention support
lib/compiler-singlepass/src/emitter_riscv.rs	RISC-V instruction emitter (not shown in diff)
lib/vm/src/trap/traphandlers.rs	Added RISC-V trap code extraction from illegal instructions
lib/compiler-singlepass/src/unwind.rs	RISC-V DWARF unwinding support
tests/compilers/issues.rs	Test adaptations for RISC-V limitations and Cranelift workaround
lib/compiler-singlepass/Cargo.toml	Added tempfile dependency and riscv feature flag
.cargo/config.toml	RISC-V cross-compilation and QEMU runner configuration
.github/workflows/build.yml	CI integration for RISC-V WAST test suite
lib/compiler-singlepass/README.md	Updated documentation to list riscv64 as experimental target

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[marxin]

The PR received a couple of fixed that very identified and reduced from running the RISC-V Singlepass compiler on tests for the following Rust crates:

• aho-corasick
• bstr
• bytesize
• glob
• indexmap
• itertools
• itoa
• memchr
• quickcheck
• rustc-demangle
• rust-shlex
• rust-url
• ryu
• strsim-rs
• strum
• time
• tinyvec
• unicode-ident
• uuid